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authorRichard Henderson <richard.henderson@linaro.org>2018-02-20 10:49:54 -0800
committerRichard Henderson <richard.henderson@linaro.org>2018-05-14 14:54:24 -0700
commit032de4fc38b9d1bac933c3be7f95b16c60db5cea (patch)
tree0689156f1ebaab2b9b3f17ab77fc18daa2a90248 /target
parentfbb3e29aace97a3c51c7ed434dfa799e7ba7f652 (diff)
target/openrisc: Convert dec_compi
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/openrisc/insns.decode12
-rw-r--r--target/openrisc/translate.c116
2 files changed, 70 insertions, 58 deletions
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode
index 29d28ff5be..4ec0e2de3a 100644
--- a/target/openrisc/insns.decode
+++ b/target/openrisc/insns.decode
@@ -21,6 +21,7 @@
&da d a
&ab a b
&dal d a l
+&ai a i
####
# System Instructions
@@ -154,3 +155,14 @@ l_sfgts 111001 01010 a:5 b:5 -----------
l_sfges 111001 01011 a:5 b:5 -----------
l_sflts 111001 01100 a:5 b:5 -----------
l_sfles 111001 01101 a:5 b:5 -----------
+
+l_sfeqi 101111 00000 a:5 i:s16
+l_sfnei 101111 00001 a:5 i:s16
+l_sfgtui 101111 00010 a:5 i:s16
+l_sfgeui 101111 00011 a:5 i:s16
+l_sfltui 101111 00100 a:5 i:s16
+l_sfleui 101111 00101 a:5 i:s16
+l_sfgtsi 101111 01010 a:5 i:s16
+l_sfgesi 101111 01011 a:5 i:s16
+l_sfltsi 101111 01100 a:5 i:s16
+l_sflesi 101111 01101 a:5 i:s16
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 8743b5e96e..c4256518cb 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1117,70 +1117,74 @@ static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond)
return true;
}
-static void dec_compi(DisasContext *dc, uint32_t insn)
+static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- uint32_t op0, ra;
- int32_t I16;
-
- op0 = extract32(insn, 21, 5);
- ra = extract32(insn, 16, 5);
- I16 = sextract32(insn, 0, 16);
-
- switch (op0) {
- case 0x0: /* l.sfeqi */
- LOG_DIS("l.sfeqi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], I16);
- break;
-
- case 0x1: /* l.sfnei */
- LOG_DIS("l.sfnei r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], I16);
- break;
+ LOG_DIS("l.sfeqi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- case 0x2: /* l.sfgtui */
- LOG_DIS("l.sfgtui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], I16);
- break;
+static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfnei r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- case 0x3: /* l.sfgeui */
- LOG_DIS("l.sfgeui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], I16);
- break;
+static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgtui r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- case 0x4: /* l.sfltui */
- LOG_DIS("l.sfltui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], I16);
- break;
+static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgeui r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- case 0x5: /* l.sfleui */
- LOG_DIS("l.sfleui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], I16);
- break;
+static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfltui r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- case 0xa: /* l.sfgtsi */
- LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], I16);
- break;
+static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfleui r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- case 0xb: /* l.sfgesi */
- LOG_DIS("l.sfgesi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], I16);
- break;
+static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgtsi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- case 0xc: /* l.sfltsi */
- LOG_DIS("l.sfltsi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], I16);
- break;
+static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgesi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- case 0xd: /* l.sflesi */
- LOG_DIS("l.sflesi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], I16);
- break;
+static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfltsi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
- default:
- gen_illegal_exception(dc);
- break;
- }
+static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sflesi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
}
static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn)
@@ -1469,10 +1473,6 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
op0 = extract32(insn, 26, 6);
switch (op0) {
- case 0x2f:
- dec_compi(dc, insn);
- break;
-
case 0x32:
dec_float(dc, insn);
break;