diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-24 18:25:25 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:43:35 -0700 |
| commit | e6cb03548850f14d3236003ae8fd33ab8b95f4ca (patch) | |
| tree | c4578d352632a5a32eaedbd7be26e5b98b085850 /target | |
| parent | fd77911304ec3b6881e7e714d5b643693b0ff1ab (diff) | |
target/microblaze: Convert dec_rts to decodetree
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/microblaze/insns.decode | 5 | ||||
| -rw-r--r-- | target/microblaze/translate.c | 51 |
2 files changed, 28 insertions, 28 deletions
diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode index e6a61f147a..8906058a29 100644 --- a/target/microblaze/insns.decode +++ b/target/microblaze/insns.decode @@ -202,6 +202,11 @@ rsubic 001011 ..... ..... ................ @typeb rsubik 001101 ..... ..... ................ @typeb rsubikc 001111 ..... ..... ................ @typeb +rtbd 101101 10010 ..... ................ @typeb_bc +rtid 101101 10001 ..... ................ @typeb_bc +rted 101101 10100 ..... ................ @typeb_bc +rtsd 101101 10000 ..... ................ @typeb_bc + sb 110100 ..... ..... ..... 0000 000 0000 @typea sbr 110100 ..... ..... ..... 0100 000 0000 @typea sbea 110100 ..... ..... ..... 0001 000 0000 @typea diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b8dcef8f1c..6c1855b29a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1252,6 +1252,29 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg) return true; } +static bool do_rts(DisasContext *dc, arg_typeb_bc *arg, int to_set) +{ + if (trap_userspace(dc, to_set)) { + return true; + } + dc->tb_flags_to_set |= to_set; + setup_dslot(dc, true); + + dc->jmp_cond = TCG_COND_ALWAYS; + dc->jmp_dest = -1; + tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, arg->ra), arg->imm); + return true; +} + +#define DO_RTS(NAME, IFLAG) \ + static bool trans_##NAME(DisasContext *dc, arg_typeb_bc *arg) \ + { return do_rts(dc, arg, IFLAG); } + +DO_RTS(rtbd, DRTB_FLAG) +DO_RTS(rtid, DRTI_FLAG) +DO_RTS(rted, DRTE_FLAG) +DO_RTS(rtsd, 0) + static bool trans_zero(DisasContext *dc, arg_zero *arg) { /* If opcode_0_illegal, trap. */ @@ -1527,33 +1550,6 @@ static inline void do_rte(DisasContext *dc) dc->tb_flags &= ~DRTE_FLAG; } -static void dec_rts(DisasContext *dc) -{ - unsigned int b_bit, i_bit, e_bit; - - i_bit = dc->ir & (1 << 21); - b_bit = dc->ir & (1 << 22); - e_bit = dc->ir & (1 << 23); - - if (trap_userspace(dc, i_bit || b_bit || e_bit)) { - return; - } - - setup_dslot(dc, true); - - if (i_bit) { - dc->tb_flags |= DRTI_FLAG; - } else if (b_bit) { - dc->tb_flags |= DRTB_FLAG; - } else if (e_bit) { - dc->tb_flags |= DRTE_FLAG; - } - - dc->jmp_cond = TCG_COND_ALWAYS; - dc->jmp_dest = -1; - tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); -} - static void dec_null(DisasContext *dc) { if (trap_illegal(dc, true)) { @@ -1601,7 +1597,6 @@ static struct decoder_info { }; void (*dec)(DisasContext *dc); } decinfo[] = { - {DEC_RTS, dec_rts}, {DEC_MSR, dec_msr}, {DEC_STREAM, dec_stream}, {{0, 0}, dec_null} |