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| author | Taylor Simpson <tsimpson@quicinc.com> | 2022-11-08 08:28:57 -0800 |
|---|---|---|
| committer | Taylor Simpson <tsimpson@quicinc.com> | 2022-12-16 10:10:28 -0800 |
| commit | 83853ea0efee80f8c39a73753a048a769a02a2c7 (patch) | |
| tree | afe2308fa30b2bad1190a513e5e148fb7a82aa8c /target/xtensa | |
| parent | 1e536334ccb0a1606f814a38a4996b3b818e9fab (diff) | |
Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur
Here are example instructions with a predicated .tmp/.cur assignment
if (p1) v12.tmp = vmem(r7 + #0)
if (p0) v12.cur = vmem(r9 + #0)
The .tmp/.cur indicates that references to v12 in the same packet
take the result of the load. However, when the predicate is false,
the value at the start of the packet should be used. After the packet
commits, the .tmp value is dropped, but the .cur value is maintained.
To fix this bug, we preload the original value from the HVX register
into the temporary used for the result.
Test cases added to tests/tcg/hexagon/hvx_misc.c
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20221108162906.3166-3-tsimpson@quicinc.com>
Diffstat (limited to 'target/xtensa')
0 files changed, 0 insertions, 0 deletions