diff options
author | Lluís Vilanova <vilanova@ac.upc.edu> | 2017-07-14 11:17:35 +0300 |
---|---|---|
committer | Richard Henderson <rth@twiddle.net> | 2017-07-19 14:45:16 -0700 |
commit | 9c489ea6bed134fecfd556b439c68bba48fbe102 (patch) | |
tree | 3d54a182709bc45c16e276cc33e36f01cbe7f4ee /target/xtensa | |
parent | 797ed66d29909e9564b146a4a181005fc8096c69 (diff) |
tcg: Pass generic CPUState to gen_intermediate_code()
Needed to implement a target-agnostic gen_intermediate_code()
in the future.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/xtensa')
-rw-r--r-- | target/xtensa/translate.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 263002486c..f3f0ff589c 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) } } -void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - XtensaCPU *cpu = xtensa_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUXtensaState *env = cs->env_ptr; DisasContext dc; int insn_count = 0; int max_insns = tb->cflags & CF_COUNT_MASK; |