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| author | Max Filippov <jcmvbkbc@gmail.com> | 2018-08-30 17:55:33 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-10-01 11:08:35 -0700 |
| commit | f473019a97d7c890ddb816367dc9f89fdfefa22e (patch) | |
| tree | f1bef085cd648c7f5dd0d4e3a202bf0dc5cb14d5 /target/xtensa/translate.c | |
| parent | 6416d16f7544c53ccb6ce7d74e8f01f502b558d3 (diff) | |
target/xtensa: extract test for window underflow exception
- mark retw and retw.n instructions;
- extract window inderflow test from retw helper;
- put underflow exception check generation right after the overflow
check;
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/translate.c')
| -rw-r--r-- | target/xtensa/translate.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 83e107a2ac..187de7467f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1071,6 +1071,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) return; } + if (op_flags & XTENSA_OP_UNDERFLOW) { + TCGv_i32 tmp = tcg_const_i32(dc->pc); + + gen_helper_test_underflow_retw(cpu_env, tmp); + tcg_temp_free(tmp); + } + for (slot = 0; slot < slots; ++slot) { XtensaOpcodeOps *ops = slot_prop[slot].ops; @@ -3485,10 +3492,12 @@ static const XtensaOpcodeOps core_ops[] = { .name = "retw", .translate = translate_retw, .test_ill = test_ill_retw, + .op_flags = XTENSA_OP_UNDERFLOW, }, { .name = "retw.n", .translate = translate_retw, .test_ill = test_ill_retw, + .op_flags = XTENSA_OP_UNDERFLOW, }, { .name = "rfdd", .op_flags = XTENSA_OP_ILL, |