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authorMax Filippov <jcmvbkbc@gmail.com>2018-04-27 13:07:53 -0700
committerMax Filippov <jcmvbkbc@gmail.com>2018-06-30 11:58:02 -0700
commitf40385c959d01bf33a0e3c12ef0fdb402ad98a1c (patch)
tree24398a0e9854be44bb97140b817723cff0a1c463 /target/xtensa/translate.c
parente3800998e66c13b24d8cc8a06fdcc8d03cd408fc (diff)
target/xtensa: check zero overhead loop alignment
ISA book documents that the first instruction of zero overhead loop must fit completely into naturally aligned region of an instruction fetch unit size. Check that condition and log a message if it's violated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/translate.c')
-rw-r--r--target/xtensa/translate.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index a11162eebe..7dd8b55d4a 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -970,6 +970,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
}
dc->next_pc = dc->pc + len;
+ if (xtensa_option_enabled(dc->config, XTENSA_OPTION_LOOP) &&
+ dc->lbeg == dc->pc &&
+ ((dc->pc ^ (dc->next_pc - 1)) & -dc->config->inst_fetch_width)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "unaligned first instruction of a loop (pc = %08x)\n",
+ dc->pc);
+ }
for (i = 1; i < len; ++i) {
b[i] = cpu_ldub_code(env, dc->pc + i);
}