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| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-03-13 12:41:13 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-05-10 16:53:55 -0700 |
| commit | 631a77a03bc8905790af6fe3fd44c6c7ff285c73 (patch) | |
| tree | f8a7eb14d17ce686f1a9ff7b863f7f745f7d4410 /target/xtensa/overlay_tool.h | |
| parent | 944bb3320aeea6285d495b645f4700c3a20668e8 (diff) | |
target/xtensa: add parity/ECC option SRs
Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option.
The implementation is trivial since we don't emulate parity/ECC yet.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/overlay_tool.h')
| -rw-r--r-- | target/xtensa/overlay_tool.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 8b380ce5e3..ffaab4b094 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -112,6 +112,8 @@ XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ + XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \ + XTENSA_OPTION_MEMORY_ECC_PARITY) | \ /* Memory protection and translation */ \ XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ XTENSA_OPTION_REGION_PROTECTION) | \ |