diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-01-23 19:26:52 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-01-24 10:44:26 -0800 |
| commit | fa92bd4af71bed76bf57bb1c8b5465414a52ab3f (patch) | |
| tree | 3beaed635eff3b55e6d6809aa579547c748e68af /target/xtensa/op_helper.c | |
| parent | fff7bf145045ec57be6bd3bdd69de7930137654c (diff) | |
target/xtensa: fix access to the INTERRUPT SR
INTERRUPT special register may be changed both by the core (by writing
to INTSET and INTCLEAR registers) and by external events (by triggering
and clearing HW IRQs). In MTTCG this state must be protected from
concurrent access, otherwise interrupts may be lost or spurious
interrupts may be detected.
Use atomic operations to change INTSET SR.
Fix wsr.intset so that it soesn't clear any bits.
Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/op_helper.c')
| -rw-r--r-- | target/xtensa/op_helper.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 1865f46c4b..04971b044f 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -62,6 +62,8 @@ void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i) { uint64_t dcc; + atomic_and(&env->sregs[INTSET], + ~(1u << env->config->timerint[i])); HELPER(update_ccount)(env); dcc = (uint64_t)(env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] - 1) + 1; timer_mod(env->ccompare[i].timer, |