diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2018-08-19 19:27:21 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-09-17 11:05:26 -0700 |
| commit | 76b7dd641fad4ab8c35f647cffe0fd47c4302b72 (patch) | |
| tree | 36c2aed5e09164e9af58b54de1495c844514e193 /target/xtensa/helper.c | |
| parent | 9a124b69279de00fc36662a5bad00159fc682965 (diff) | |
target/xtensa: convert to do_transaction_failed
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/helper.c')
| -rw-r--r-- | target/xtensa/helper.c | 30 |
1 files changed, 23 insertions, 7 deletions
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f74636f678..4fceb4424a 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -566,7 +566,7 @@ static bool is_access_granted(unsigned access, int is_write) } } -static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); +static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, uint32_t vaddr, int is_write, int mmu_idx, @@ -584,7 +584,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && - may_lookup_pt && get_pte(env, vaddr, &pte) == 0) { + may_lookup_pt && get_pte(env, vaddr, &pte)) { ring = (pte >> 4) & 0x3; wi = 0; split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); @@ -631,7 +631,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, return 0; } -static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) +static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) { CPUState *cs = CPU(xtensa_env_get_cpu(env)); uint32_t paddr; @@ -642,13 +642,29 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, &paddr, &page_size, &access, false); - qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n", - __func__, vaddr, ret ? ~0 : paddr); + if (ret == 0) { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n", + __func__, vaddr, pt_vaddr, paddr); + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n", + __func__, vaddr, pt_vaddr, ret); + } if (ret == 0) { - *pte = ldl_phys(cs->as, paddr); + MemTxResult result; + + *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, + &result); + if (result != MEMTX_OK) { + qemu_log_mask(CPU_LOG_MMU, + "%s: couldn't load PTE: transaction failed (%u)\n", + __func__, (unsigned)result); + ret = 1; + } } - return ret; + return ret == 0; } static int get_physical_addr_region(CPUXtensaState *env, |