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| author | Max Filippov <jcmvbkbc@gmail.com> | 2020-07-11 02:58:22 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2020-08-21 12:48:15 -0700 |
| commit | de6b55cbda2a26fb8889c8a8b44c139d7e106dce (patch) | |
| tree | 39226f6cfb491940e5f0b88fd1ff4f60bd6072e1 /target/xtensa/cpu.h | |
| parent | 5dbb4c96d50c6ef74d4fd71a5a0fd9763d5a3662 (diff) | |
target/xtensa: add DFPU option
Double precision floating point unit is a FPU implementation different
from the FPU2000 in the following ways:
- it may be configured with only single or with both single and double
precision operations support;
- it may be configured with division and square root opcodes;
- FSR register accumulates inValid, division by Zero, Overflow,
Underflow and Inexact result flags of operations;
- QNaNs and SNaNs are handled properly;
- NaN propagation rules are different.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.h')
| -rw-r--r-- | target/xtensa/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 960f657344..6fc1565000 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -52,6 +52,8 @@ enum { XTENSA_OPTION_COPROCESSOR, XTENSA_OPTION_BOOLEAN, XTENSA_OPTION_FP_COPROCESSOR, + XTENSA_OPTION_DFP_COPROCESSOR, + XTENSA_OPTION_DFPU_SINGLE_ONLY, XTENSA_OPTION_MP_SYNCHRO, XTENSA_OPTION_CONDITIONAL_STORE, XTENSA_OPTION_ATOMCTL, |