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| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-03-13 12:41:13 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-05-10 16:53:55 -0700 |
| commit | 631a77a03bc8905790af6fe3fd44c6c7ff285c73 (patch) | |
| tree | f8a7eb14d17ce686f1a9ff7b863f7f745f7d4410 /target/xtensa/cpu.h | |
| parent | 944bb3320aeea6285d495b645f4700c3a20668e8 (diff) | |
target/xtensa: add parity/ECC option SRs
Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option.
The implementation is trivial since we don't emulate parity/ECC yet.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.h')
| -rw-r--r-- | target/xtensa/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d4258fcc61..74ee7d1253 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -144,6 +144,12 @@ enum { CACHEATTR = 98, ATOMCTL = 99, DDR = 104, + MEPC = 106, + MEPS = 107, + MESAVE = 108, + MESR = 109, + MECR = 110, + MEVADDR = 111, IBREAKA = 128, DBREAKA = 144, DBREAKC = 160, |