target/xtensa: sim: instantiate local memories

Xtensa core may have a number of RAM and ROM areas configured. Record
their size and location from the core configuration overlay and
instantiate them as RAM regions in the SIM machine.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 7e7131a596..ecca17d45d 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -212,6 +212,7 @@ enum {
 #define MAX_NCCOMPARE 3
 #define MAX_TLB_WAY_SIZE 8
 #define MAX_NDBREAK 2
+#define MAX_NMEMORY 4
 
 #define REGION_PAGE_MASK 0xe0000000
 
@@ -321,6 +322,14 @@ typedef struct XtensaCcompareTimer {
     QEMUTimer *timer;
 } XtensaCcompareTimer;
 
+typedef struct XtensaMemory {
+    unsigned num;
+    struct XtensaMemoryRegion {
+        uint32_t addr;
+        uint32_t size;
+    } location[MAX_NMEMORY];
+} XtensaMemory;
+
 struct XtensaConfig {
     const char *name;
     uint64_t options;
@@ -352,6 +361,13 @@ struct XtensaConfig {
     unsigned dcache_ways;
     uint32_t memctl_mask;
 
+    XtensaMemory instrom;
+    XtensaMemory instram;
+    XtensaMemory datarom;
+    XtensaMemory dataram;
+    XtensaMemory sysrom;
+    XtensaMemory sysram;
+
     uint32_t configid[2];
 
     uint32_t clock_freq_khz;