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authorPeter Maydell <peter.maydell@linaro.org>2022-11-24 11:50:22 +0000
committerPeter Maydell <peter.maydell@linaro.org>2022-12-16 15:58:16 +0000
commitd66e64dd006dfbc08f5395e1ca674903d46fa601 (patch)
tree0171b9f1c9fc18aa691893ea788a86326ab01b8b /target/xtensa/cpu.c
parentefcc10682e8a1feda4c6b2766cb7067e58f75135 (diff)
target/xtensa: Convert to 3-phase reset
Convert the xtensa CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20221124115023.2437291-20-peter.maydell@linaro.org
Diffstat (limited to 'target/xtensa/cpu.c')
-rw-r--r--target/xtensa/cpu.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 09923301c4..2dc8f2d232 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -85,16 +85,18 @@ bool xtensa_abi_call0(void)
}
#endif
-static void xtensa_cpu_reset(DeviceState *dev)
+static void xtensa_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(dev);
+ CPUState *s = CPU(obj);
XtensaCPU *cpu = XTENSA_CPU(s);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
CPUXtensaState *env = &cpu->env;
bool dfpu = xtensa_option_enabled(env->config,
XTENSA_OPTION_DFP_COPROCESSOR);
- xcc->parent_reset(dev);
+ if (xcc->parent_phases.hold) {
+ xcc->parent_phases.hold(obj);
+ }
env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
env->sregs[LITBASE] &= ~1;
@@ -240,11 +242,13 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
&xcc->parent_realize);
- device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
+ resettable_class_set_parent_phases(rc, NULL, xtensa_cpu_reset_hold, NULL,
+ &xcc->parent_phases);
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;