diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2016-11-11 22:40:18 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2017-01-15 13:01:56 -0800 |
| commit | 9e03ade4411c81a7f7d974dcedf0390835ce4096 (patch) | |
| tree | 5ed7163044ac610d041277e20def7990e507b1b5 /target/xtensa/cpu.c | |
| parent | 4b37aaa879d508494df14bdc49830cdf8aa77a57 (diff) | |
target/xtensa: implement MEMCTL SR
MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/cpu.c')
| -rw-r--r-- | target/xtensa/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 1c18892fca..811d8780d6 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -66,6 +66,7 @@ static void xtensa_cpu_reset(CPUState *s) XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; + env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; |