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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-01-25 16:36:57 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-01-25 16:36:57 +0000 |
| commit | e32c41e4f65f4d16508fe759a800538a73608839 (patch) | |
| tree | 288ad9c192a4d6b58d3490eb088450de7153922c /target/xtensa/cpu.c | |
| parent | ae5045ae5b2bbd8ce1335d1b05f9ecacca83a6cf (diff) | |
| parent | 3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02 (diff) | |
Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into staging
target/xtensa updates:
- refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting);
- support icount; run target/xtensa TCG tests with icount;
- implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER.
# gpg: Signature made Wed 25 Jan 2017 00:27:51 GMT
# gpg: using RSA key 0x51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20170124-xtensa:
target-xtensa: implement RER/WER instructions
target/xtensa: tests: clean up interrupt tests
target/xtensa: tests: add memctl test
target/xtensa: implement MEMCTL SR
target/xtensa: fix ICACHE/DCACHE options detection
target/xtensa: tests: add ccount write tests
target/xtensa: tests: replace hardcoded interrupt masks
target/xtensa: tests: fix timer tests
target/xtensa: tests: run tests with icount
target/xtensa: don't continue translation after exception
target/xtensa: support icount
target/xtensa: refactor CCOUNT/CCOMPARE
target/xtensa: implement RUNSTALL
target/xtensa: add static vectors selection
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/xtensa/cpu.c')
| -rw-r--r-- | target/xtensa/cpu.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e8e9f9175b..cd7f95823f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -47,7 +47,7 @@ static bool xtensa_cpu_has_work(CPUState *cs) { XtensaCPU *cpu = XTENSA_CPU(cs); - return cpu->env.pending_irq_level; + return !cpu->env.runstall && cpu->env.pending_irq_level; } /* CPUClass::reset() */ @@ -60,12 +60,13 @@ static void xtensa_cpu_reset(CPUState *s) xcc->parent_reset(s); env->exception_taken = 0; - env->pc = env->config->exception_vector[EXC_RESET]; + env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors]; env->sregs[LITBASE] &= ~1; env->sregs[PS] = xtensa_option_enabled(env->config, XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; + env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; @@ -74,6 +75,7 @@ static void xtensa_cpu_reset(CPUState *s) env->pending_irq_level = 0; reset_mmu(env); + s->halted = env->runstall; } static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) @@ -125,6 +127,12 @@ static void xtensa_cpu_initfn(Object *obj) cs->env_ptr = env; env->config = xcc->config; + env->address_space_er = g_malloc(sizeof(*env->address_space_er)); + env->system_er = g_malloc(sizeof(*env->system_er)); + memory_region_init_io(env->system_er, NULL, NULL, env, "er", + UINT64_C(0x100000000)); + address_space_init(env->address_space_er, env->system_er, "ER"); + if (tcg_enabled() && !tcg_inited) { tcg_inited = true; xtensa_translate_init(); |