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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-05-21 10:44:21 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-05-21 10:44:21 +0100 |
| commit | 293c76cb48332d2bbd70bd975dc60ee3650b3170 (patch) | |
| tree | dd0c752de59da7520cec044c2fcc8bfba869da30 /target/xtensa/cpu.c | |
| parent | 2259637b95bef3116cc262459271de08e038cc66 (diff) | |
| parent | b345e140534ea17814b02bdf8798f18db6295304 (diff) | |
Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging
target/xtensa: SR reorganization and options for modern cores
Reorganize special register handling to support configurations with
conflicting SR definitions.
Implement options used by the modern xtensa cores:
- memory protection unit;
- block prefetch;
- exclusive access
Add special register definitions and IRQ types for ECC/parity,
gather/scatter and IDMA.
# gpg: Signature made Mon 20 May 2019 18:53:05 BST
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20190520-xtensa:
target/xtensa: implement exclusive access option
target/xtensa: update list of exception causes
target/xtensa: implement block prefetch option opcodes
target/xtensa: implement DIWBUI.P opcode
target/xtensa: implement MPU option
target/xtensa: add parity/ECC option SRs
target/xtensa: define IDMA and gather/scatter IRQ types
target/xtensa: make internal MMU functions static
target/xtensa: get rid of centralized SR properties
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/xtensa/cpu.c')
| -rw-r--r-- | target/xtensa/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index da1236377e..c79dc75bfe 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -78,11 +78,11 @@ static void xtensa_cpu_reset(CPUState *s) env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; - env->sregs[CACHEATTR] = 0x22222222; env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; env->sregs[CONFIGID0] = env->config->configid[0]; env->sregs[CONFIGID1] = env->config->configid[1]; + env->exclusive_addr = -1; #ifndef CONFIG_USER_ONLY reset_mmu(env); |