diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2021-03-05 14:06:38 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2021-03-14 14:49:01 +0100 |
| commit | a21993c7f98862823280d1eb6d3e93cf6267896f (patch) | |
| tree | 95cba878e0753b1816e70c6f5a47de812d0e0416 /target/tricore | |
| parent | 007479842b27e03173a333b8c2e0dae14be64f8d (diff) | |
target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
if width was 0 we would run into the assertion:
qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o
The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/tricore')
| -rw-r--r-- | target/tricore/translate.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 5b7ed70e39..2a814263de 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -7000,6 +7000,11 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RRPW_EXTR: + if (width == 0) { + tcg_gen_movi_tl(cpu_gpr_d[r3], 0); + break; + } + if (pos + width <= 32) { /* optimize special cases */ if ((pos == 0) && (width == 8)) { |