diff options
| author | David Brenken <david.brenken@efs-auto.de> | 2018-03-01 16:56:18 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2018-03-02 11:46:34 +0100 |
| commit | d1cbc28ae155310bce27765d09d7fa4a2d2b831b (patch) | |
| tree | 4b8fafc8f499a0dfb586d75501749d4f7c6748a0 /target/tricore | |
| parent | 04e62411caa3560fd0c684820875fa86b934904b (diff) | |
tricore: renamed masking of IE
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Florian Artmeier <florian.artmeier@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Message-Id: <20180301155619.8640-4-david.brenken@efs-auto.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/tricore')
| -rw-r--r-- | target/tricore/cpu.h | 3 | ||||
| -rw-r--r-- | target/tricore/op_helper.c | 17 | ||||
| -rw-r--r-- | target/tricore/translate.c | 4 |
3 files changed, 13 insertions, 11 deletions
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 045126181a..6d89f625d0 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -256,7 +256,8 @@ void tricore_cpu_dump_state(CPUState *cpu, FILE *f, #define MASK_CPUID_REV 0x000000ff #define MASK_ICR_PIPN 0x00ff0000 -#define MASK_ICR_IE 0x00000100 +#define MASK_ICR_IE_1_3 0x00000100 +#define MASK_ICR_IE_1_6 0x00008000 #define MASK_ICR_CCPN 0x000000ff #define MASK_FCX_FCXS 0x000f0000 diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 098f217c2a..475b6ce081 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -85,7 +85,7 @@ raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin, /* PCXI.PIE = ICR.IE */ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.PCPN = ICR.CCPN */ env->PCXI = (env->PCXI & 0xffffff) + ((env->ICR & MASK_ICR_CCPN) << 24); @@ -2465,7 +2465,7 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc) ((env->ICR & MASK_ICR_CCPN) << 24); /* PCXI.PIE = ICR.IE; */ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.UL = 1; */ env->PCXI |= MASK_PCXI_UL; @@ -2563,7 +2563,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9) ((env->ICR & MASK_ICR_CCPN) << 24); /* PCXI.PIE = ICR.IE */ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.UL = 0 */ env->PCXI &= ~(MASK_PCXI_UL); /* PCXI[19: 0] = FCX[19: 0] */ @@ -2571,7 +2571,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9) /* FXC[19: 0] = new_FCX[19: 0] */ env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff); /* ICR.IE = 1 */ - env->ICR |= MASK_ICR_IE; + env->ICR |= MASK_ICR_IE_1_3; env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/ @@ -2603,7 +2603,8 @@ void helper_rfe(CPUTriCoreState *env) } env->PC = env->gpr_a[11] & ~0x1; /* ICR.IE = PCXI.PIE; */ - env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15); + env->ICR = (env->ICR & ~MASK_ICR_IE_1_3) + + ((env->PCXI & MASK_PCXI_PIE) >> 15); /* ICR.CCPN = PCXI.PCPN; */ env->ICR = (env->ICR & ~MASK_ICR_CCPN) + ((env->PCXI & MASK_PCXI_PCPN) >> 24); @@ -2627,7 +2628,7 @@ void helper_rfm(CPUTriCoreState *env) { env->PC = (env->gpr_a[11] & ~0x1); /* ICR.IE = PCXI.PIE; */ - env->ICR = (env->ICR & ~MASK_ICR_IE) | + env->ICR = (env->ICR & ~MASK_ICR_IE_1_3) | ((env->PCXI & MASK_PCXI_PIE) >> 15); /* ICR.CCPN = PCXI.PCPN; */ env->ICR = (env->ICR & ~MASK_ICR_CCPN) | @@ -2694,7 +2695,7 @@ void helper_svlcx(CPUTriCoreState *env) ((env->ICR & MASK_ICR_CCPN) << 24); /* PCXI.PIE = ICR.IE; */ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.UL = 0; */ env->PCXI &= ~MASK_PCXI_UL; @@ -2737,7 +2738,7 @@ void helper_svucx(CPUTriCoreState *env) ((env->ICR & MASK_ICR_CCPN) << 24); /* PCXI.PIE = ICR.IE; */ env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE) + - ((env->ICR & MASK_ICR_IE) << 15)); + ((env->ICR & MASK_ICR_IE_1_3) << 15)); /* PCXI.UL = 1; */ env->PCXI |= MASK_PCXI_UL; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 54de0dd346..aef0d9cf06 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8379,12 +8379,12 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) /* raise EXCP_DEBUG */ break; case OPC2_32_SYS_DISABLE: - tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE); + tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); break; case OPC2_32_SYS_DSYNC: break; case OPC2_32_SYS_ENABLE: - tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE); + tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3); break; case OPC2_32_SYS_ISYNC: break; |