diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-02-02 13:04:25 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-02-08 09:57:42 +0100 |
| commit | 1c6b2e4b794d460a16a7f94cf6a7d6864f708be1 (patch) | |
| tree | 776e2e4d573a027694557dec77a54c8f8b529f8b /target/tricore | |
| parent | 76f7f54840abef8f712e51d87ecb38f27a0d9db0 (diff) | |
target/tricore: Fix OPC2_32_RCRW_INSERT translation
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-4-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/tricore')
| -rw-r--r-- | target/tricore/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 8de4e56b1f..6149d4f5c0 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5805,8 +5805,8 @@ static void decode_rcrw_insert(DisasContext *ctx) tcg_gen_movi_tl(temp, width); tcg_gen_movi_tl(temp2, const4); - tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f); - gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3); + tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); + gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); tcg_temp_free(temp3); break; |