diff options
author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2019-08-21 11:02:23 +0200 |
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committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2019-08-22 12:16:58 +0200 |
commit | 17ebc8c1047a9c9f07c25585156231d34fd4a682 (patch) | |
tree | 76f2c6182ed3e3a14dda977d4fbda043ebe7ec89 /target/tricore/translate.c | |
parent | 1fae1851e5b35437ac22b46b6786b084fffb8cf2 (diff) |
target/tricore: Implement a qemu excptions helper
this helper is only used to raise qemu specific exceptions. We use this
helper to raise it on breakpoints.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/tricore/translate.c')
-rw-r--r-- | target/tricore/translate.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 5fb42abe35..88b2840ad1 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -3261,6 +3261,15 @@ static void generate_trap(DisasContext *ctx, int class, int tin) tcg_temp_free(tintemp); } +static void generate_qemu_excp(DisasContext *ctx, int excp) +{ + TCGv_i32 tmp = tcg_const_i32(excp); + gen_save_pc(ctx->base.pc_next); + gen_helper_qemu_excp(cpu_env, tmp); + ctx->base.is_jmp = DISAS_NORETURN; + tcg_temp_free(tmp); +} + static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, TCGv r2, int16_t address) { @@ -8808,7 +8817,16 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, const CPUBreakpoint *bp) { - return false; + DisasContext *ctx = container_of(dcbase, DisasContext, base); + generate_qemu_excp(ctx, EXCP_DEBUG); + /* + * The address covered by the breakpoint must be included in + * [tb->pc, tb->pc + tb->size) in order to for it to be + * properly cleared -- thus we increment the PC here so that + * the logic setting tb->size below does the right thing. + */ + ctx->base.pc_next += 4; + return true; } static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |