diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2023-11-04 15:23:35 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2024-06-05 09:05:53 -0700 |
commit | 1d3ed3d728f81dee4ae87028a8a3e9beb4fa4a17 (patch) | |
tree | ad4af833969d7152f7e5d98dfc518915b68eb285 /target/sparc/translate.c | |
parent | 3d50b7287e3c11b769945fd7352788d69b1a5a5e (diff) |
target/sparc: Implement FLCMP
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/sparc/translate.c')
-rw-r--r-- | target/sparc/translate.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d81b9ce5a8..db3a153c6e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5207,6 +5207,40 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e) TRANS(FCMPq, ALL, do_fcmpq, a, false) TRANS(FCMPEq, ALL, do_fcmpq, a, true) +static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) +{ + TCGv_i32 src1, src2; + + if (!avail_VIS3(dc)) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + src1 = gen_load_fpr_F(dc, a->rs1); + src2 = gen_load_fpr_F(dc, a->rs2); + gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); + return advance_pc(dc); +} + +static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) +{ + TCGv_i64 src1, src2; + + if (!avail_VIS3(dc)) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); + return advance_pc(dc); +} + static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); |