diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-02-24 21:26:59 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-03-05 13:44:08 -0800 |
| commit | 36ab4623a894de80c413fa958a5fdb79dc50b1c2 (patch) | |
| tree | 544b574d62f10c855ba4af17b71fea6a31ac8163 /target/sparc/translate.c | |
| parent | 52123f14e14233a353f81f87506b3b8c7b38898c (diff) | |
target/sparc: Drop get_temp_i32
Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new_i32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/sparc/translate.c')
| -rw-r--r-- | target/sparc/translate.c | 23 |
1 files changed, 3 insertions, 20 deletions
diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2b4af692f6..a20426202e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -84,8 +84,6 @@ typedef struct DisasContext { uint32_t cc_op; /* current CC operation */ sparc_def_t *def; - TCGv_i32 t32[3]; - int n_t32; #ifdef TARGET_SPARC64 int fprs_dirty; int asi; @@ -129,14 +127,6 @@ static int sign_extend(int x, int len) #define IS_IMM (insn & (1<<13)) -static inline TCGv_i32 get_temp_i32(DisasContext *dc) -{ - TCGv_i32 t; - assert(dc->n_t32 < ARRAY_SIZE(dc->t32)); - dc->t32[dc->n_t32++] = t = tcg_temp_new_i32(); - return t; -} - static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) { #if defined(TARGET_SPARC64) @@ -153,7 +143,7 @@ static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) /* floating point registers moves */ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) { - TCGv_i32 ret = get_temp_i32(dc); + TCGv_i32 ret = tcg_temp_new_i32(); if (src & 1) { tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]); } else { @@ -175,7 +165,7 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) static TCGv_i32 gen_dest_fpr_F(DisasContext *dc) { - return get_temp_i32(dc); + return tcg_temp_new_i32(); } static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) @@ -5516,7 +5506,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; } #endif - cpu_dst_32 = get_temp_i32(dc); + cpu_dst_32 = tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, dc->mem_idx, MO_TEUL); gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32); @@ -5763,13 +5753,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto egress; #endif egress: - if (dc->n_t32 != 0) { - int i; - for (i = dc->n_t32 - 1; i >= 0; --i) { - tcg_temp_free_i32(dc->t32[i]); - } - dc->n_t32 = 0; - } } static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |