diff options
| author | Richard Henderson <rth@twiddle.net> | 2017-07-18 10:02:42 -1000 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2017-07-18 23:39:17 +0200 |
| commit | bdcb3739024f3b6d53bd6dc34eaeafb3f2b996d9 (patch) | |
| tree | 2cc1661cb2b92544eef73ac888d476fb469daa86 /target/sh4/translate.c | |
| parent | 4d57fa50d5208b92a06b0e08c32cc0bb7ab75aaf (diff) | |
target/sh4: Simplify 64-bit fp reg-reg move
We do not need to form full 64-bit quantities in order to perform
the move. This reduces code expansion on 64-bit hosts.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-18-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target/sh4/translate.c')
| -rw-r--r-- | target/sh4/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 7dfe23d1f4..792a46804b 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -981,10 +981,10 @@ static void _decode_opc(DisasContext * ctx) case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, XHACK(B7_4)); - gen_store_fpr64(ctx, fp, XHACK(B11_8)); - tcg_temp_free_i64(fp); + int xsrc = XHACK(B7_4); + int xdst = XHACK(B11_8); + tcg_gen_mov_i32(FREG(xdst), FREG(xsrc)); + tcg_gen_mov_i32(FREG(xdst + 1), FREG(xsrc + 1)); } else { tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4)); } |