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authorDavid Hildenbrand <david@redhat.com>2018-03-01 13:08:26 +0100
committerCornelia Huck <cohuck@redhat.com>2018-03-01 13:23:09 +0100
commitbe8b49de2491145a7aad3201803327b6f568cbd3 (patch)
treebcf7c25e20bafa952ce6541552112a9cba1ef664 /target/s390x
parenteae9f29130f3ed40ad77f40a3bae4b9ebff28907 (diff)
s390x/tcg: fix loading 31bit PSWs with the highest bit set
Let's also put the 31-bit hack in front of the REAL MMU, otherwise right now we get errors when loading a PSW where the highest bit is set (e.g. via s390-netboot.img). The highest bit is not masked away, therefore we inject addressing exceptions into the guest. The proper fix will later be to do all address wrapping before accessing the MMU - so we won't get any "wrong" entries in there (which makes flushing also easier). But that will require more work (wrapping in load_psw, wrapping when incrementing the PC, wrapping every memory access). This fixes the tests/pxe-test test. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180301120826.6847-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x')
-rw-r--r--target/s390x/excp_helper.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 411051edc3..dfee221111 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -107,6 +107,10 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
return 1;
}
} else if (mmu_idx == MMU_REAL_IDX) {
+ /* 31-Bit mode */
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ vaddr &= 0x7fffffff;
+ }
if (mmu_translate_real(env, vaddr, rw, &raddr, &prot)) {
return 1;
}