diff options
| author | David Hildenbrand <david@redhat.com> | 2019-03-07 13:15:36 +0100 |
|---|---|---|
| committer | Cornelia Huck <cohuck@redhat.com> | 2019-03-11 09:31:01 +0100 |
| commit | 7b9a236ea70f92c261206e4b120f57b0c68462cd (patch) | |
| tree | e5f99b44a2fb7d97a3fc506a6a04448b3c487776 /target/s390x | |
| parent | 15e12add0b1256f3e699541c2eb8320e0f63a02d (diff) | |
s390x/tcg: Implement VECTOR STORE ELEMENT
As we only store one element, there is nothing to consider regarding
exceptions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20190307121539.12842-30-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x')
| -rw-r--r-- | target/s390x/insn-data.def | 5 | ||||
| -rw-r--r-- | target/s390x/translate_vx.inc.c | 18 |
2 files changed, 23 insertions, 0 deletions
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 4525d5b145..ff5b9e7302 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1036,6 +1036,11 @@ F(0xe75f, VSEG, VRR_a, V, 0, 0, 0, 0, vseg, 0, IF_VEC) /* VECTOR STORE */ F(0xe70e, VST, VRX, V, la2, 0, 0, 0, vst, 0, IF_VEC) +/* VECTOR STORE ELEMENT */ + E(0xe708, VSTEB, VRX, V, la2, 0, 0, 0, vste, 0, ES_8, IF_VEC) + E(0xe709, VSTEH, VRX, V, la2, 0, 0, 0, vste, 0, ES_16, IF_VEC) + E(0xe70b, VSTEF, VRX, V, la2, 0, 0, 0, vste, 0, ES_32, IF_VEC) + E(0xe70a, VSTEG, VRX, V, la2, 0, 0, 0, vste, 0, ES_64, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index fcddd0cde7..ecc295da5b 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -834,3 +834,21 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps *o) tcg_temp_free_i64(tmp); return DISAS_NEXT; } + +static DisasJumpType op_vste(DisasContext *s, DisasOps *o) +{ + const uint8_t es = s->insn->data; + const uint8_t enr = get_field(s->fields, m3); + TCGv_i64 tmp; + + if (!valid_vec_element(enr, es)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + tmp = tcg_temp_new_i64(); + read_vec_element_i64(tmp, get_field(s->fields, v1), enr, es); + tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); + tcg_temp_free_i64(tmp); + return DISAS_NEXT; +} |