diff options
author | David Hildenbrand <david@redhat.com> | 2021-06-08 11:23:31 +0200 |
---|---|---|
committer | Cornelia Huck <cohuck@redhat.com> | 2021-06-21 08:48:21 +0200 |
commit | a38b5a0eab9538543a241582d80cf0eb6ce97f1f (patch) | |
tree | f93ea86c4f8424e586d6d4616f2d1ca10847b3a6 /target/s390x/vec_fpu_helper.c | |
parent | 390eeb35757ffeeed6811370625e11a1c6b1d565 (diff) |
s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-21-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x/vec_fpu_helper.c')
-rw-r--r-- | target/s390x/vec_fpu_helper.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c index 0fb82bd18f..6984f770ff 100644 --- a/target/s390x/vec_fpu_helper.c +++ b/target/s390x/vec_fpu_helper.c @@ -622,6 +622,36 @@ void HELPER(gvec_##NAME##BITS)(void *v1, const void *v2, const void *v3, \ DEF_GVEC_VFMA(vfma, 0) DEF_GVEC_VFMA(vfms, float_muladd_negate_c) +void HELPER(gvec_vftci32)(void *v1, const void *v2, CPUS390XState *env, + uint32_t desc) +{ + uint16_t i3 = extract32(simd_data(desc), 4, 12); + bool s = extract32(simd_data(desc), 3, 1); + int i, match = 0; + + for (i = 0; i < 4; i++) { + float32 a = s390_vec_read_float32(v2, i); + + if (float32_dcmask(env, a) & i3) { + match++; + s390_vec_write_element32(v1, i, -1u); + } else { + s390_vec_write_element32(v1, i, 0); + } + if (s) { + break; + } + } + + if (match == 4 || (s && match)) { + env->cc_op = 0; + } else if (match) { + env->cc_op = 1; + } else { + env->cc_op = 3; + } +} + void HELPER(gvec_vftci64)(void *v1, const void *v2, CPUS390XState *env, uint32_t desc) { @@ -651,3 +681,20 @@ void HELPER(gvec_vftci64)(void *v1, const void *v2, CPUS390XState *env, env->cc_op = 3; } } + +void HELPER(gvec_vftci128)(void *v1, const void *v2, CPUS390XState *env, + uint32_t desc) +{ + const float128 a = s390_vec_read_float128(v2); + uint16_t i3 = extract32(simd_data(desc), 4, 12); + + if (float128_dcmask(env, a) & i3) { + env->cc_op = 0; + s390_vec_write_element64(v1, 0, -1ull); + s390_vec_write_element64(v1, 1, -1ull); + } else { + env->cc_op = 3; + s390_vec_write_element64(v1, 0, 0); + s390_vec_write_element64(v1, 1, 0); + } +} |