diff options
author | David Hildenbrand <david@redhat.com> | 2018-01-15 00:29:22 +0100 |
---|---|---|
committer | David Hildenbrand <david@redhat.com> | 2019-10-09 12:49:01 +0200 |
commit | 3a06f981925bfade8f5e650655fce0b38dbd6649 (patch) | |
tree | fe4f3d4e4cdf8b89f6f89a6551eb09c45ac52054 /target/s390x/mmu_helper.c | |
parent | 3dc29061f3291bf0b6cda9cc7bc04aa94101b52e (diff) |
s390x/mmu: Implement Instruction-Execution-Protection Facility
IEP support in the mmu is fairly easy. Set the right permissions for TLB
entries and properly report an exception.
Make sure to handle EDAT-2 by setting bit 56/60/61 of the TEID (TEC) to
the right values.
Let's keep s390_cpu_get_phys_page_debug() working even if IEP is
active. Switch MMU_DATA_LOAD - this has no other effects any more as the
ASC to be used is now fully selected outside of mmu_translate().
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
Diffstat (limited to 'target/s390x/mmu_helper.c')
-rw-r--r-- | target/s390x/mmu_helper.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 06502bd25d..4a794dadcf 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -121,6 +121,8 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, const bool edat1 = (env->cregs[0] & CR0_EDAT) && s390_has_feat(S390_FEAT_EDAT); const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2); + const bool iep = (env->cregs[0] & CR0_IEP) && + s390_has_feat(S390_FEAT_INSTRUCTION_EXEC_PROT); const int asce_tl = asce & ASCE_TABLE_LENGTH; const int asce_p = asce & ASCE_PRIVATE_SPACE; hwaddr gaddr = asce & ASCE_ORIGIN; @@ -225,6 +227,9 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, *flags &= ~PAGE_WRITE; } if (edat2 && (entry & REGION3_ENTRY_FC)) { + if (iep && (entry & REGION3_ENTRY_IEP)) { + *flags &= ~PAGE_EXEC; + } *raddr = (entry & REGION3_ENTRY_RFAA) | (vaddr & ~REGION3_ENTRY_RFAA); return 0; @@ -252,6 +257,9 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, *flags &= ~PAGE_WRITE; } if (edat1 && (entry & SEGMENT_ENTRY_FC)) { + if (iep && (entry & SEGMENT_ENTRY_IEP)) { + *flags &= ~PAGE_EXEC; + } *raddr = (entry & SEGMENT_ENTRY_SFAA) | (vaddr & ~SEGMENT_ENTRY_SFAA); return 0; @@ -272,6 +280,9 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, if (entry & PAGE_ENTRY_P) { *flags &= ~PAGE_WRITE; } + if (iep && (entry & PAGE_ENTRY_IEP)) { + *flags &= ~PAGE_EXEC; + } *raddr = entry & TARGET_PAGE_MASK; return 0; @@ -430,6 +441,16 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, return -1; } + /* check for Instruction-Execution-Protection */ + if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) { + if (exc) { + /* IEP sets bit 56 and 61 */ + tec |= 0x84; + trigger_access_exception(env, PGM_PROTECTION, ilen, tec); + } + return -1; + } + nodat: /* Convert real address -> absolute address */ *raddr = mmu_real2abs(env, *raddr); |