diff options
| author | Janosch Frank <frankja@linux.ibm.com> | 2019-12-03 08:28:12 -0500 |
|---|---|---|
| committer | Cornelia Huck <cohuck@redhat.com> | 2019-12-14 10:25:50 +0100 |
| commit | e893baee70149896d1e43e341da4d6c614037d5d (patch) | |
| tree | 6cd005e2bc8880753e636764756fa85029db9c91 /target/s390x/cpu.h | |
| parent | 15b6c0370c3e2774fd9ffda5c10c6e36952e8eb6 (diff) | |
s390x: Fix cpu normal reset ri clearing
As it turns out we need to clear the ri controls and PSW enablement
bit to be architecture compliant.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com>
Message-Id: <20191203132813.2734-4-frankja@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x/cpu.h')
| -rw-r--r-- | target/s390x/cpu.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index d2af13b345..7e1c18d596 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -58,7 +58,6 @@ struct CPUS390XState { */ uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ uint32_t aregs[16]; /* access registers */ - uint8_t riccb[64]; /* runtime instrumentation control */ uint64_t gscb[4]; /* guarded storage control */ uint64_t etoken; /* etoken */ uint64_t etoken_extension; /* etoken extension */ @@ -114,6 +113,10 @@ struct CPUS390XState { uint64_t gbea; uint64_t pp; + /* Fields up to this point are not cleared by normal CPU reset */ + struct {} start_normal_reset_fields; + uint8_t riccb[64]; /* runtime instrumentation control */ + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -252,6 +255,7 @@ extern const VMStateDescription vmstate_s390_cpu; #undef PSW_SHIFT_ASC #undef PSW_MASK_CC #undef PSW_MASK_PM +#undef PSW_MASK_RI #undef PSW_SHIFT_MASK_PM #undef PSW_MASK_64 #undef PSW_MASK_32 @@ -273,6 +277,7 @@ extern const VMStateDescription vmstate_s390_cpu; #define PSW_MASK_CC 0x0000300000000000ULL #define PSW_MASK_PM 0x00000F0000000000ULL #define PSW_SHIFT_MASK_PM 40 +#define PSW_MASK_RI 0x0000008000000000ULL #define PSW_MASK_64 0x0000000100000000ULL #define PSW_MASK_32 0x0000000080000000ULL #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL |