diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-17 09:51:30 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-04-21 10:04:34 -0700 |
| commit | 3c69336a8773ec9dde145d40f3e715b9395e0aa0 (patch) | |
| tree | a52d61cb2c6cf9192d45f15e2cf2e5ffbc3c5cfa /target/rx | |
| parent | d3562fe2588d3e0a15f3785d86792800d717984c (diff) | |
target/rx: Swap stack pointers on clrpsw/setpsw instruction
We properly perform this swap in helper_set_psw for MVTC,
but we missed doing so for the CLRPSW/SETPSW of the U bit.
Reported-by: Tomoaki Kawada <i@yvt.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20220417165130.695085-5-richard.henderson@linaro.org>
Diffstat (limited to 'target/rx')
| -rw-r--r-- | target/rx/translate.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/target/rx/translate.c b/target/rx/translate.c index bd4d110e8b..63c062993e 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2165,7 +2165,12 @@ static inline void clrsetpsw(DisasContext *ctx, int cb, int val) ctx->base.is_jmp = DISAS_UPDATE; break; case PSW_U: - tcg_gen_movi_i32(cpu_psw_u, val); + if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) { + ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val); + tcg_gen_movi_i32(cpu_psw_u, val); + tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp); + tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp); + } break; default: qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); |