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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-17 17:15:08 +0800 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 17:06:39 +1000 |
commit | dc7b599332c26065cd9ff1f2f2cf3ed580ca3dfd (patch) | |
tree | 7d020eeda81742b034b0ba2be7c7b3f26a7440d8 /target/rx/cpu.c | |
parent | faf3b5d86ff3b0349ded42f8ef3240d1960b6a1a (diff) |
target/riscv: Update pmp_get_tlb_size()
PMP entries before (including) the matched PMP entry may only cover partial
of the TLB page, and this may split the page into regions with different
permissions. Such as for PMP0 (0x80000008~0x8000000F, R) and PMP1 (0x80000000~
0x80000FFF, RWX), write access to 0x80000000 will match PMP1. However we cannot
cache the translation result in the TLB since this will make the write access
to 0x80000008 bypass the check of PMP0. So we should check all of them instead
of the matched PMP entry in pmp_get_tlb_size() and set the tlb_size to 1 in
this case.
Set tlb_size to TARGET_PAGE_SIZE if PMP is not support or there is no PMP rules.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/rx/cpu.c')
0 files changed, 0 insertions, 0 deletions