diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2018-06-08 13:15:33 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-06-08 13:15:33 +0100 |
| commit | 0cd3f644feda1fc6c7c370c97a91df4552a69548 (patch) | |
| tree | 17fca1c037ab3ef815415b43d220484917466111 /target/riscv | |
| parent | 21528149eba03fc17f428a8e1660d8666683ca85 (diff) | |
RISC-V: Add trailing '\n' to qemu_log() calls
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180606152128.449-11-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/op_helper.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3abf52453c..aec7558e1b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -293,7 +293,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, if ((val_to_write & 3) == 0) { env->stvec = val_to_write >> 2 << 2; } else { - qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported"); + qemu_log_mask(LOG_UNIMP, + "CSR_STVEC: vectored traps not supported\n"); } break; case CSR_SCOUNTEREN: @@ -320,7 +321,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, if ((val_to_write & 3) == 0) { env->mtvec = val_to_write >> 2 << 2; } else { - qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported"); + qemu_log_mask(LOG_UNIMP, + "CSR_MTVEC: vectored traps not supported\n"); } break; case CSR_MCOUNTEREN: |