diff options
| author | Emmanuel Blot <emmanuel.blot@sifive.com> | 2021-04-21 15:32:36 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-05-11 20:02:07 +1000 |
| commit | 6cfcf77573fb9714afd09b9b9ead05e002102243 (patch) | |
| tree | 922be9bc1136a3737993efec4b0b989353a2958b /target/riscv | |
| parent | 3a7f7757ba95a374f73ed08cd5a9af366299ef81 (diff) | |
target/riscv: fix a typo with interrupt names
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4bf6a00636..04ac03f8c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = { "vs_timer", "m_timer", "u_external", + "s_external", "vs_external", - "h_external", "m_external", "reserved", "reserved", |