diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-06-15 14:32:57 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-07-10 22:29:15 +1000 |
| commit | 4556fdaa5cb7157b9adb3ee136f44d5952b94736 (patch) | |
| tree | 2613263a156803390ca0bcd0ab84d30f4dc0d282 /target/riscv | |
| parent | 9e1c7d982d7feb5b6547276ecc4c10468c0f5092 (diff) | |
target/riscv: Add properties for BF16 extensions
Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
Add require check for BF16 extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230615063302.102409-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 20 | ||||
| -rw-r--r-- | target/riscv/cpu_cfg.h | 3 |
2 files changed, 23 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0c9faf4633..0272b1d071 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1118,6 +1118,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfbfmin extension depends on F extension"); + return; + } + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { error_setg(errp, "D extension requires F extension"); return; @@ -1168,6 +1173,21 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); + return; + } + + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); + return; + } + + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); + return; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zhinx) { cpu->cfg.ext_zhinxmin = true; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 6b7e736bc2..e9ee39d7de 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -75,6 +75,7 @@ struct RISCVCPUConfig { bool ext_svpbmt; bool ext_zdinx; bool ext_zawrs; + bool ext_zfbfmin; bool ext_zfh; bool ext_zfhmin; bool ext_zfinx; @@ -84,6 +85,8 @@ struct RISCVCPUConfig { bool ext_zve64f; bool ext_zve64d; bool ext_zmmul; + bool ext_zvfbfmin; + bool ext_zvfbfwma; bool ext_zvfh; bool ext_zvfhmin; bool ext_smaia; |