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authorRichard Henderson <richard.henderson@linaro.org>2020-09-15 17:46:37 -0700
committerEduardo Habkost <ehabkost@redhat.com>2020-09-18 13:59:51 -0400
commit5de5b99b3101a1648ed583193db8d92eea0c4545 (patch)
treedc7076689fbdf2f5d4ed851c7a1f95f1965905bc /target/riscv
parent1b49d14459958dbc8b9f5cd44b43b440a9c9c62b (diff)
target/riscv: Set instance_align on RISCVCPU TypeInfo
Fix alignment of CPURISCVState.vreg. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200916004638.2444147-6-richard.henderson@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/cpu.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 57c006df5d..0bbfd7f457 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -628,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.name = TYPE_RISCV_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(RISCVCPU),
+ .instance_align = __alignof__(RISCVCPU),
.instance_init = riscv_cpu_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),