diff options
author | Hiroaki Yamamoto <hrak1529@gmail.com> | 2024-02-28 17:10:28 +0900 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2024-03-08 20:48:03 +1000 |
commit | 6979b7b3f242c44a4908a5fe83f424aa852648a3 (patch) | |
tree | d4d6d11e31cd55777d556744cc6752dc8501fa25 /target/riscv | |
parent | 0678e9f29c2301d0a1afc8d01a78cdfa7ad2ddbd (diff) |
target/riscv: Fix privilege mode of G-stage translation for debugging
G-stage translation should be considered to be user-level access in
riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill().
This fixes a bug that prevents gdb from reading memory while the VM is
running in VS-mode.
Signed-off-by: Hiroaki Yamamoto <hrak1529@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240228081028.35081-1-hrak1529@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r-- | target/riscv/cpu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c994a72634..ce7322011d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1223,7 +1223,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) if (env->virt_enabled) { if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, - 0, mmu_idx, false, true, true)) { + 0, MMUIdx_U, false, true, true)) { return -1; } } |