diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-07 09:47:42 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 44b8f74b0088df22f30e0718f6aefa9fb87702f6 (patch) | |
| tree | 10f29752d34a2c3f63ff349dec28707324b00185 /target/riscv | |
| parent | 04803c3ddb37a8c84392452c3596bd1c4474904d (diff) | |
target/riscv: Use PRV_RESERVED instead of PRV_H
PRV_H has no real meaning, but just a reserved privilege mode currently.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn>
[ Changes by AF:
- Convert one missing use of PRV_H
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 2 | ||||
| -rw-r--r-- | target/riscv/cpu_bits.h | 2 | ||||
| -rw-r--r-- | target/riscv/cpu_helper.c | 2 | ||||
| -rw-r--r-- | target/riscv/gdbstub.c | 2 | ||||
| -rw-r--r-- | target/riscv/op_helper.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f47c3fc139..86e08d10da 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -684,7 +684,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) case PRV_U: xl = get_field(env->mstatus, MSTATUS64_UXL); break; - default: /* PRV_S | PRV_H */ + default: /* PRV_S */ xl = get_field(env->mstatus, MSTATUS64_SXL); break; } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 101702cb4a..a16bfaf43f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -608,7 +608,7 @@ typedef enum { /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 -#define PRV_H 2 /* Reserved */ +#define PRV_RESERVED 2 #define PRV_M 3 /* RV32 satp CSR field masks */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2310c7905f..29ac7956f7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -650,7 +650,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) if (newpriv > PRV_M) { g_assert_not_reached(); } - if (newpriv == PRV_H) { + if (newpriv == PRV_RESERVED) { newpriv = PRV_U; } if (icount_enabled() && newpriv != env->priv) { diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index fa537aed74..524bede865 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -203,7 +203,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) if (n == 0) { #ifndef CONFIG_USER_ONLY cs->priv = ldtul_p(mem_buf) & 0x3; - if (cs->priv == PRV_H) { + if (cs->priv == PRV_RESERVED) { cs->priv = PRV_S; } #endif diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index b8a03afebb..bd21c6eeef 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -141,7 +141,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits, } if (env->virt_enabled && - (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) || + (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) || ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); } |