diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:05:34 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 15:17:52 -0800 |
| commit | 732b902dd5803e3cb228424050300beffe097acf (patch) | |
| tree | b0bab96c6a0119400bbeae56a4b8718557706c3e /target/riscv | |
| parent | 3f4a5a5314b1d2d1fe910b87a3784743993003da (diff) | |
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
Check for Zve32f/Zve64d can overlap check for F/D.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-10-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 6f7ecf1a68..9b2711b94b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -41,9 +41,9 @@ static bool require_rvf(DisasContext *s) switch (s->sew) { case MO_16: case MO_32: - return has_ext(s, RVF); + return s->cfg_ptr->ext_zve32f; case MO_64: - return has_ext(s, RVD); + return s->cfg_ptr->ext_zve64d; default: return false; } @@ -58,9 +58,9 @@ static bool require_scale_rvf(DisasContext *s) switch (s->sew) { case MO_8: case MO_16: - return has_ext(s, RVF); + return s->cfg_ptr->ext_zve32f; case MO_32: - return has_ext(s, RVD); + return s->cfg_ptr->ext_zve64d; default: return false; } |