diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-05-17 17:15:14 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 17:11:38 +1000 |
| commit | 37e79058031b0490734f724edf4e1691f6b3601e (patch) | |
| tree | f7e1baac961b325f549d88e8d06e4cd6036beb0e /target/riscv | |
| parent | 97ec5aef082d8b40a0a37d4d6274ffe165ef27b7 (diff) | |
target/riscv: Flush TLB when MMWP or MML bits are changed
MMWP and MML bits may affect the allowed privs of PMP entries and the
default privs, both of which may change the allowed privs of exsited
TLB entries. So we need flush TLB when they are changed.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517091519.34439-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/pmp.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 2403039133..4d62dfc732 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -578,6 +578,9 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val) if (riscv_cpu_cfg(env)->epmp) { /* Sticky bits */ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); + if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { + tlb_flush(env_cpu(env)); + } } else { val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); } |