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authorAlistair Francis <alistair.francis@wdc.com>2020-01-31 17:02:38 -0800
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-02-27 13:45:45 -0800
commit0736febb2d0e1bb503ca07091c16a16e78480366 (patch)
treee2e63cbab2817b4cb1b02059448859872006d47a /target/riscv
parent895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a (diff)
target/riscv: Remove the hret instruction
The hret instruction does not exist in the new spec versions, so remove it from QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/insn32.decode1
-rw-r--r--target/riscv/insn_trans/trans_privileged.inc.c5
2 files changed, 0 insertions, 6 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index cfd9ca6d2b..b883672e63 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -75,7 +75,6 @@ ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011
uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011
-hret 0010000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
index b9b5a89b52..76c2fad71c 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -58,11 +58,6 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
#endif
}
-static bool trans_hret(DisasContext *ctx, arg_hret *a)
-{
- return false;
-}
-
static bool trans_mret(DisasContext *ctx, arg_mret *a)
{
#ifndef CONFIG_USER_ONLY