diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:05:31 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 15:17:38 -0800 |
| commit | 2e60f9ec2ccb3906323deda7797f91c74b967b3f (patch) | |
| tree | d3909a7562b7bf636559da4ec52bab41a624bc2f /target/riscv | |
| parent | e7f0a803a7b98a784ec6bce7992b7ad643881150 (diff) | |
target/riscv: Add property check for Zvfh{min} extensions
Add check for Zvfh and Zvfhmin.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-7-liweiwei@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 49912c9174..49ac368662 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -768,6 +768,20 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvfh) { + cpu->cfg.ext_zvfhmin = true; + } + + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); + return; + } + + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { + error_setg(errp, "Zvfh extensions requires Zfhmin extension"); + return; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_zhinx) { cpu->cfg.ext_zhinxmin = true; |