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| author | Bin Meng <bmeng.cn@gmail.com> | 2020-07-16 02:30:56 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-07-22 09:39:46 -0700 |
| commit | e79d27cb322b60b460b709d2c74ff7d77cde0565 (patch) | |
| tree | 68cd5478640ed930427eba0646e3bf19b1093e50 /target/riscv | |
| parent | 3e09396e36dff4234afd6f6fd51861949be383e1 (diff) | |
hw/riscv: sifive_e: Correct debug block size
Currently the debug region size is set to 0x100, but according to
FE310-G000 and FE310-G002 manuals:
FE310-G000: 0x100 - 0xFFF
FE310-G002: 0x0 - 0xFFF
Change the size to 0x1000 that applies to both.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
0 files changed, 0 insertions, 0 deletions