diff options
| author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:53 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:19 +1000 |
| commit | 91870b510ae5d1cb9688231b8f01dceaab64de68 (patch) | |
| tree | ba65ce0852fb058178a1cdd33194cf1879276718 /target/riscv | |
| parent | d207863cd3ed056055e2324a4abe47f54e7c6384 (diff) | |
target/riscv: Allow users to force enable AIA CSRs in HART
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 5 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5fb0a61036..9dce57a380 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -537,6 +537,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } + if (cpu->cfg.aia) { + riscv_set_feature(env, RISCV_FEATURE_AIA); + } + set_resetvec(env, cpu->cfg.resetvec); /* Validate that MISA_MXL is set properly. */ @@ -782,6 +786,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c70de10c85..7ecb1387dd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -376,6 +376,7 @@ struct RISCVCPUConfig { bool mmu; bool pmp; bool epmp; + bool aia; uint64_t resetvec; }; |