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author | Richard Henderson <richard.henderson@linaro.org> | 2021-01-28 14:55:57 -1000 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:14 -1000 |
commit | 552672bae63dd2c470fc533f276b746bae90b813 (patch) | |
tree | c20d9b1658b033f2689686c3ffe68d32ad7e0389 /target/riscv | |
parent | 187f44d9da0ca8ac08451f03f62b259080596570 (diff) |
tcg/tci: Fix TCG_REG_R4 misusage
This was removed from tcg_target_reg_alloc_order and
tcg_target_call_iarg_regs on the assumption that it
was the stack. This was incorrectly copied from i386.
For tci, the stack is R15.
By adding R4 back to tcg_target_call_iarg_regs, adjust the other
entries so that 6 (or 12) entries are still present in the array,
and adjust the numbers in the interpreter.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv')
0 files changed, 0 insertions, 0 deletions