diff options
| author | Atish Patra <atishp@rivosinc.com> | 2022-08-24 15:13:55 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-09-07 09:19:10 +0200 |
| commit | 7cbcc538f4b3040db1e39a6547efa501a8a44907 (patch) | |
| tree | ec5d8fafc780421b1060979e4ef45221f0b98b91 /target/riscv | |
| parent | dc9acc9ce4add37bc5b4437ae9117c318b4f09d4 (diff) | |
hw/intc: Move mtimer/mtimecmp to aclint
Historically, The mtime/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.
Move them to the ACLINT device. This also emulates the real hardware
more closely.
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 2 | ||||
| -rw-r--r-- | target/riscv/machine.c | 5 |
2 files changed, 2 insertions, 5 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 081cd05544..53335def23 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -307,7 +307,6 @@ struct CPUArchState { /* temporary htif regs */ uint64_t mfromhost; uint64_t mtohost; - uint64_t timecmp; /* physical memory protection */ pmp_table_t pmp_state; @@ -362,7 +361,6 @@ struct CPUArchState { float_status fp_status; /* Fields from here on are preserved across CPU reset. */ - QEMUTimer *timer; /* Internal timer */ hwaddr kernel_addr; hwaddr fdt_addr; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index dc182ca811..b508b042cb 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -307,8 +307,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 3, - .minimum_version_id = 3, + .version_id = 4, + .minimum_version_id = 4, .post_load = riscv_cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -359,7 +359,6 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU), VMSTATE_UINT64(env.mtohost, RISCVCPU), - VMSTATE_UINT64(env.timecmp, RISCVCPU), VMSTATE_END_OF_LIST() }, |