diff options
| author | Kito Cheng <kito.cheng@gmail.com> | 2019-03-26 17:27:17 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-03-26 03:17:30 -0700 |
| commit | 620455350a8da7cc62ae82cb69dd5c556f744136 (patch) | |
| tree | d6fa9ea50e3a9e1d2361869b8273881fdfdaa9df /target/riscv | |
| parent | 4aef51963924fd58ffe88daebbe8055a360d7c10 (diff) | |
target/riscv: Fix wrong expanding for c.fswsp
base register is no rs1 not rs2 for fsw.
Signed-off-by: Kito Cheng <kito.cheng@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvc.inc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c index 5819f53f90..ebcd977b2f 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -337,7 +337,7 @@ static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) { #ifdef TARGET_RISCV32 /* C.FSWSP */ - arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp }; + arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp }; return trans_fsw(ctx, &a_fsw); #else /* C.SDSP */ |