diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-24 12:08:47 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 17:28:13 -0800 |
| commit | 73ec0ead67ca8b4b10132b033b7388d0718b2353 (patch) | |
| tree | df49173b12f0151f71928784f5f925d8f0cea22e /target/riscv | |
| parent | 627634031092e1514f363fd8659a579398de0f0e (diff) | |
target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions
menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-2-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/csr.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1b0a0c1693..b20b00a9a7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1885,10 +1885,12 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno, static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPUConfig *cfg = &env_archcpu(env)->cfg; uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; if (riscv_cpu_mxl(env) == MXL_RV64) { - mask |= MENVCFG_PBMTE | MENVCFG_STCE; + mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | + (cfg->ext_sstc ? MENVCFG_STCE : 0); } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); @@ -1905,7 +1907,9 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; + RISCVCPUConfig *cfg = &env_archcpu(env)->cfg; + uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | + (cfg->ext_sstc ? MENVCFG_STCE : 0); uint64_t valh = (uint64_t)val << 32; env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); |