aboutsummaryrefslogtreecommitdiff
path: root/target/riscv
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2021-10-19 20:17:01 -0700
committerAlistair Francis <alistair@alistair23.me>2021-10-22 07:47:51 +1000
commit4e97d459a0f2b92815c2c2c6eb96b75e2235b42e (patch)
tree7d34d475c80cee99fb6fd111bf95d4b931004dfe /target/riscv
parentfbb48032e46976cfc94a90a4233a2060fdc36a4e (diff)
target/riscv: Properly check SEW in amo_op
We're currently assuming SEW <= 3, and the "else" from the SEW == 3 must be less. Use a switch and explicitly bound both SEW and SEQ for all cases. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-8-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/insn_trans/trans_rvv.c.inc26
1 files changed, 14 insertions, 12 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 233131bae1..17ee3babef 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_exit_atomic(cpu_env);
s->base.is_jmp = DISAS_NORETURN;
return true;
- } else {
- if (s->sew == 3) {
- if (!is_32bit(s)) {
- fn = fnsd[seq];
- } else {
- /* Check done in amo_check(). */
- g_assert_not_reached();
- }
- } else {
- assert(seq < ARRAY_SIZE(fnsw));
- fn = fnsw[seq];
- }
+ }
+
+ switch (s->sew) {
+ case 0 ... 2:
+ assert(seq < ARRAY_SIZE(fnsw));
+ fn = fnsw[seq];
+ break;
+ case 3:
+ /* XLEN check done in amo_check(). */
+ assert(seq < ARRAY_SIZE(fnsd));
+ fn = fnsd[seq];
+ break;
+ default:
+ g_assert_not_reached();
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);