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authorFrank Chang <frank.chang@sifive.com>2021-04-19 14:03:01 +0800
committerAlistair Francis <alistair.francis@wdc.com>2021-05-11 20:02:07 +1000
commitb11e84b883bf9b790732a03703559bf4797ad272 (patch)
tree51ddf348967e8e980e13d4789eefa441210d25bb /target/riscv/vector_helper.c
parented6eebaaafd3b96cc4ef3dcc30eb3a26c20ece57 (diff)
target/riscv: fix vrgather macro index variable type bug
ETYPE may be type of uint64_t, thus index variable has to be declared as type of uint64_t, too. Otherwise the value read from vs1 register may be truncated to type of uint32_t. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210419060302.14075-1-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/vector_helper.c')
-rw-r--r--target/riscv/vector_helper.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 356cef8a09..4651a1e224 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4796,7 +4796,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t index, i; \
+ uint64_t index; \
+ uint32_t i; \
\
for (i = 0; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
@@ -4826,7 +4827,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t index = s1, i; \
+ uint64_t index = s1; \
+ uint32_t i; \
\
for (i = 0; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, mlen, i)) { \