diff options
| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:57:00 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:53:31 +1000 |
| commit | 26086aea0d4f5575c0b66acd05ccb41349f8a32d (patch) | |
| tree | 9695b84df954fa0be8cf43dd08a0d6d0d4edfdef /target/riscv/vector_helper.c | |
| parent | 5c89e9c0966dd423207bc477fcda9eb454d4308f (diff) | |
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-75-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/vector_helper.c')
| -rw-r--r-- | target/riscv/vector_helper.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 83373ca6fc..4c1a1310e6 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -346,6 +346,27 @@ GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) /* + *** unit stride mask load and store, EEW = 1 + */ +void HELPER(vlm_v)(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc) +{ + /* evl = ceil(vl/8) */ + uint8_t evl = (env->vl + 7) >> 3; + vext_ldst_us(vd, base, env, desc, lde_b, + 0, evl, GETPC(), MMU_DATA_LOAD); +} + +void HELPER(vsm_v)(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc) +{ + /* evl = ceil(vl/8) */ + uint8_t evl = (env->vl + 7) >> 3; + vext_ldst_us(vd, base, env, desc, ste_b, + 0, evl, GETPC(), MMU_DATA_STORE); +} + +/* *** index: access vector element from indexed memory */ typedef target_ulong vext_get_index_addr(target_ulong base, |