diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-03-07 16:13:59 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-05-05 10:49:50 +1000 |
| commit | 193eb522e4083d8e84c3fae443fd98bc300b95d0 (patch) | |
| tree | 4ed4a127f94712c691fdf276b75674896839ed96 /target/riscv/translate.c | |
| parent | e0a3054f18e20602768d328b0cb7d5910253a327 (diff) | |
target/riscv: add support for Zcmp extension
Add encode, trans* functions for Zcmp instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3634137d85..6872d17fb9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -757,6 +757,11 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } +static int ex_sreg_register(DisasContext *ctx, int reg) +{ + return reg < 2 ? reg + 8 : reg + 16; +} + static int ex_rvc_shiftli(DisasContext *ctx, int imm) { /* For RV128 a shamt of 0 means a shift by 64. */ |